1. Technical Field
The present invention relates to a phase locked loop (hereinafter, referred to as PLL) circuit and a control method thereof, in particular, to a phase locked loop circuit that detects and corrects a phase difference between a reference clock and a feedback clock, and to a control method thereof.
2. Related Art
In general, a PLL circuit is a frequency feedback type circuit that generates a signal having a certain frequency in response to the frequency of an input signal. The PLL detects a phase difference between a reference signal and an oscillation signal and performs phase synchronization, such that the oscillation signal has a desired frequency, using an up-down signal according to the detected phase difference. The PLL is used as a clock recovery circuit for a frequency synthesis circuit or a data processing circuit.
Such a PLL circuit performs a phase locking operation on a clock frequency required by a system in a normal system operation mode, and stops the phase locking operation in a mode for minimizing the system power consumption, for example, in a power down mode, thereby reducing the power consumption of the PLL circuit.
When the system, that is, a semiconductor memory to which the PLL circuit is applied, enters the power down mode, the voltage level of a memory element constituting the PLL circuit may drop. For this reason, when the system returns to the normal mode again, the PLL circuit may not remember the previous state, repeat the same processes as those in the normal system operation mode, and perform a phase relocking operation on the clock frequency.
Therefore, since it takes much time for phase locking and relocking of the clock frequency, system performance deteriorates, and power consumption increases.